The Webinar on ASIC(Application Specific Integrated Circuits) and SoC(System on Chip) Workflow is organized by IBM on Aug 12; 4:30 PM.
Details of the Webinar
ASIC – Application Specific Integrated circuit. Nearly all the advances in modern day electronic systems and devices are a direct outcome of ASIC technology. ASIC is a semiconductor device designed especially for a particular customer (vs Standard Product, which is designed for general use by any customer). ASIC usually covers analog, digital and mixed-signal electronics.
The development cycle of an ASIC has different phases like design, verification, Physical Design, and Testing. However, the increasing costs associated with the development of high-end ASICs have forced a fundamental shift in the ASIC development process.
Today’s industry is moving towards faster, smaller, and more energy-efficient ASICs with increasingly high-density chip technologies with decreasing product cycle times. The two most critical parameters that have been used to measure the worth of new technologies have been speed and power.
With this increasing demand, it’s very important to focus on each and every phase of the development cycle of an ASIC, making the investment pay-off as required. The penalty for discovering an error after a chip(ASIC) is developed, is huge a major risk. Depending on the severity of the error respinning of the chip is required which involves an enormous huge cost.
Hence a thorough ASIC development cycle is very important. Our Goal in this panel is to educate people on the development cycle of an ASIC which covers different phases like design, verification, timing, physical design, and testing.
This covers various challenges we face in different phases and key points an ASIC engineer should know while designing a chip. The panel will provide an overview of the development cycle and challenges they have faced or seen in these phases.
Session Date and Time
- Date: 12th August 2021
- Time: 4:30 PM – 5:30 PM
About The Speakers
- Uma Rajagopalan – Verification Engineer with IBM, with more than 22 years of industry experience. Have been instrumental in the verification of 3 generations of Power Processors and 4 communication peripherals for IBM servers. Apart from pre-silicon verification, have worked in the post-silicon validation of some of these chips. Prior to the IBM experience, had worked as a System Development engineer in a Communication System Development company contributing to India’s Communication Boom in the late 1990s and early 2000s.
- Jayashri A B – Verification Engineer with IBM more than 22 years of Industry Experience and her key area is Front End Design and Verification for ASIC chips. Worked extensively on IBM Storage, Power Generation Series chips, and SOC. Along with this have experience in the Logic design of Memory chips.
How to Register?
Interested participants can register for the webinar through this link.
August 11, 2021