NIT Karnataka is hosting the TTTC India-VLSI Test Workshop on March 30, 2019. Register by March 24.
About the VLSI Test Symposium:
Verification and testing are the key steps in VLSI chip design cycle to ascertain their functional correctness and defect free fabrication. VLSI testing encompasses all spectrums of test methods and structures embedded in IC design to ensure the quality of manufactured devices.
The test methods typically include fault modeling, test generation, and fault simulation. The test structures often employ design for testability (DFT) techniques, such as scan design and built-in self-test (BIST).
This symposium focuses on providing participants with a basic understanding of the most recent DFT advances in logic, memory, delay and SOC testing. The talks cover wide-ranging topics in the following fields from basics to advanced level.
- Evolution of Design for the test.
- Cell-Aware Test / Defect-Oriented Test.
- Small Delay Defect Testing.
- Emerging Automotive Electronic Industry and Associated Test Challenges.
- IEEE 1687 IJTAG.
Who can Attend?
The symposium is open to students, faculty and working professionals with basic knowledge of VLSI Design.
Lecture Hall Complex C, Western Campus, National Institute of Technology Karnataka Surathkal, Karnataka.
How to Register?
Kindly register through this link.
The number of seats is limited to 70. A mail will be sent across on 27th March 2019 requesting confirmation from your end and acknowledgment to that mail is mandatory to confirm your registration. A final confirmation mail will be sent on 28th March 2019.
For more information, click here.