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TCE Madurai workshop 2019

Workshop on Schematic to GDSII File Generation at Thiagarajar College of Engineering, Madurai [Oct 11-12]: Registrations Open

The aim of this workshop is to provide hands-on experience on the state-of-the-art Cadence EDA tools for VLSI Design. The participants will have exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive). Workshop topics Digital Design and Sign-off (Verilog/VHDL) Specifications Run Conformal Equivalence Checks Digital Implementation Synthesis and Test ASIC Physical Design Custom IC/Analog/RF Design …

Read MoreWorkshop on Schematic to GDSII File Generation at Thiagarajar College of Engineering, Madurai [Oct 11-12]: Registrations Open

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