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JOB POST: Research Positions [Monthly Stipend Upto Rs. 54K] @ SETS, Chennai: Apply by June 15: Expired

Research Positions SETS JobAbout:

Society for Electronic Transactions and Security invites applications from citizens of India for filling up the positions of Research Associate and JRF for a sponsored project from Department of Science and Technology (DST), Government of India to SETS for 3 years.

Key Functions and Responsibilities for both the posts:

  • Work with components for QKD system development
  • Realize complex FPGA design from specifications to board integration
  • (Specification, FPGA synthesis, design, validation and integration of the FPGA
  • devices)
  • Ensure functional tests of FPGA’s on developed boards and demonstrate to subject
  • matter experts
  • Work with core project group and subject matter experts
Duration:

(For both the posts) 3 years

Posts:
  1. Research Associate (Number of Posts: 1)
  2. Junior Research Fellow-JRF (Number of Posts: 2)
Eligibility:
  • Research Associate:
    • PhD in Engineering/Science in the relevant area of the project or
    • M.E/M.Tech in Microelectronics and Photonics/Laser and Electro Optics/Electronics and Communication Engineering/VLSI Design/Digital Electronics/Embedded Systems/ or equivalent from a recognized university with First Class or equivalent with at least 3 years of relevant experience.
  • Junior Research Fellow:
    • M.E/M.Tech in Electronics and Communication Engineering/Digital Electronics/Embedded Systems/VLSI Design/Microelectronics and
      Photonics/Laser and Electro Optics/ or equivalent from a recognized university with First Class or equivalent.
Desirable Skills/ Knowledge:
  1. Research Associate
    1. Knowledge of Quantum Communication and Information.
    2. Hands-on experience in optical communication interfaces.
    3. Knowledge of Xilinx FPGA implementation flow and tools.
    4. Knowledge of FPGA realization and control softwares.
  2. Junior Research Fellow
    1. Knowledge of Xilinx FPGA implementation flow and tools
    2. Hands-on experience in simulation using MATLAB/ModelSim and FPGA realization using VHDL/Verilog programming.
    3. Knowledge of clock, memory, DCM, and I/O management and implementation on FPGAs (desirable)
    4. Experience in design integration, FPGA I/O communications and testing (desirable)
Salary:
  1. Research Associate: Rs 47000 p.m. plus 24% HRA
  2. Junior Research Fellow: Rs 31000 p.m. plus 24% HRA
Increment:

The positions as proposed are purely temporary on Contract basis with consolidated salary under the project. The contract will be for 3 years. In each year, performance review shall be made to ensure continuation.

Upon satisfactory performance, RA will be paid Rs 49000 p.m. plus 24% HRA for the 2 nd year and Rs 54000 p.m. plus 24% HRA for the 3rd year. The JRF will become SRF after two years and will be paid Rs 35000 p.m. plus 24% HRA for the 3rd year. Other rules apply as per prevailing DST norms.

How to Apply:

The candidate is required to send the filled-in Personal Particulars Form (Available here) by email to hrqkd2019@setsindia.net. Candidate should write “Application for the post of ______ for QKD Project of DST” in the subject line of his/her E-mail.

Contact:

044-66632521

For more details, click here.

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