Program on Design of Analog Integrated Circuits in Nanometer CMOS at IIT Kharagpur [Jul 20-24]: Register by Jul 10: Expired

IIT Kharagpur is organising a Program on Design of Analog Integrated Circuits in Nanometer CMOS on 20-24 July 2020. Primary focus of this course is to introduce the design of analog and mixed-signal circuits in nanometer CMOS and provide hands-on experience in designing analog circuits using state-of-the-art EDA tools like Cadence. A couple of Case-Study will also be taken up so that the participants get to apply the knowledge gained to real world applications
Nanometer CMOS analog and mixed-signal design differs significantly from conventional CMOS design because of the low intrinsic device gain, small headroom, higher noise, and larger variability. This program aims at introducing conventional CMOS analog design and methods to adapt those conventional techniques to realize reliable analog front-ends in nanometer CMOS.
A couple of casestudies would also be discussed to bridge the gap between transistor-level design and analog subsystem design to meet certain system requirements. Layout techniques will also be discussed and the participants will be given a quick walk-through from Schematic-to-GDS, thus facilitating them a tape-out experience

Topics
  • Short-Channel Effects
  • Impact of Scaling
  • Single-Stage Amplifiers
  • Current Sources
  • Differential Amplifiers
  • Noise in Transistors
  • Feedback and Stability
  • Common Mode Feedback Circuit
  • Bandgap and Precision Circuits
  • Case Study I: Low Dropout Regulator (LDO)
  • Case Study II: Design of Signal Conditioning Circuit
  • Single Stage
  • Amplifier
  • Current Source
  • Noise Analysis
  • Two-stage fully differential op amp with CMFB
  • LDO Design
  • Chopper Amplifier Design
  • Layout techniques
Who can attend?

For TEQIP III Institutes: Only faculty participants. For others Teachers from Colleges/ Institutions/Universities, Scientific Officers, Instructors, Technical Assistants, Research Scholars, Under Graduate and Post Graduate Students and Partipants from Industries

Important date

Last date of registration is 10 July 2020.

Fee
  • Nil for TEQIP III Sponsered participants
  • For others :
    INR 15000/- + GST 18% (for teachers and others)
    INR 10000/- + GST 18% (for OUTSIDE students)
    INR 20000/- + GST 18% (for industry and R&D participants)
Contact

Dr. Bidhudatta Sahoo
Phone : +91-3222-283518
Email: bsahoo[at]ece.iitkgp.ac.in

For more details, click here.

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