JOB POST: Chip Power Estimation Engineer at NVIDIA, Bangalore: Apply Now!

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NVIDIA invites applications for Chip Power Estimation Engineer for the year 2021 motivated engineers willing to work on architectural power estimation.

About the Company

NVIDIA’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI  the next era of computing with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.

Today, NVIDIA is increasingly known as “the AI computing company.”

About the Job

NVIDIA is seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world’s leading GPUs and SOCs. In this position, the responsibility includes the development of advanced power models to estimate chip and board power under product-driven use cases. In this position, the responsibility includes the development of advanced power models to estimate chip and board power under product-driven use cases.

To understand the high-level chip architecture, application use-cases, low power design techniques, process technology aspects that impact dynamic and leakage power, develop the estimation infrastructure, estimate power consumption under various scenarios. Architecture, design, synthesis, timing, circuit, and post-silicon teams will be working together to accomplish tasks.

The position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

At NVIDIA, the employees are passionate about parallel and visual computing. Together in the quest to transform the way graphics are used to solve some of the most complex problems in computer science.

Key Job Resposibilities
  • Architecture, development, and correlation of power estimation models/tools for NVIDIA’s chips
  • Help architect and develop power models for use-cases, Idle power, and IO power.
  • Chip in to design the tools based on these models and their testing methodology/infrastructures
  • Correlate and Calibrate the power models using measured silicon data
  • Analyze and help decide the chip configuration and process technology options to optimize power/performance for NVIDIA’s upcoming chips
  • Help study and contribute to Performance/Watt improvement ideas for NVIDIA’s GPUs and SOCs.
Eligibility
  • B.Tech./M.Tech and 1-2 years of experience related to Power/Performance estimation and optimization techniques
  • Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits
  • Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS)
  • Strong background in power estimation techniques, flows, and algorithms
  • Good software programming skills. Python/C++ preferred. Good skills with object-oriented programming and design.
  • Exposure to lab setup including power measurement equipment such as scope/DAQ with the ability to analyze board-level power issues is a plus
  • Exposure to power analysis EDA tools such as PTPX/EPS
  • Good communication skills & desire to work as a great teammate
How to Apply?

Interested applicants can apply for the post through this link.

For more details, click the link below.

Chip Power Estimation Engineer at NVIDIA, Bangalore
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