Applications are invited from eligible candidates for the post of ASIC Digital Design Engineer at Synopsys, Mumbai.
Synopsys is an American electronic design automation company that focuses on silicon design and verification, silicon intellectual property and software security and quality.
About the Job
Seeking a highly motivated and innovative mixed signal co-simulation verification engineer manager with strong theoretical and practical background in high-speed data recovery circuits. Needs to have good people management skills.
Working as part of a highly experienced mixed-signal design team, the candidate will be involved in managing team (with some hands on work) in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3 SERDES products.
The position offers an excellent opportunity to work with an expert team of digital, analog and mixed signal engineers responsible for delivering high-end mixed-signal designs.
Remote work is optional for this position.
- Enrolled in Electrical Engineering program and have basic knowledge about analog circuitry designs such as bandgap, opamp, PLL
- Experience writing scripts in languages such as Perl, Python and Unix shell. The ideal candidate would be familiar with Verilog and System Verilog
- Managing team, making project plans, tracking it, addressing dependencies, status reporting
- modifying/using the existing UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs
- analyzing/verifying the functionalities of SERDES
- Defining and tracking verification testplans
- Debugging simulation failures in both analog and digital domains
- Creating top level analog testbenches for SERDES
- Performing physic layout reliability analysis for SERDES
How to Apply?
Interested applicants can apply for the post through this link.
Click here to view the official notification for the post of ASIC Digital Design Engineer at Synopsys, Mumbai.
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