Synopsys is an American electronic design automation company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include logic synthesis, behavioural synthesis, place and route, static timing analysis, formal verification, hardware description language (SystemC, SystemVerilog/Verilog, VHDL) simulators, as well as transistor-level circuit simulation.
Synopsys Hyderabad is inviting applications from highly interested and motivated candidates for the post of Technical Engineering Interns.
- Bachelor’s degree in engineering is required as a minimum.
- Requires 0+ years of related experience.
- Good Digital Design Knowledge is a must.
- Microprocessor architecture knowledge is a big plus.
- Good written, verbal and analytical skills desired.
- Experience in the following areas is preferred:
- HDL and Verification languages: SystemVerilog, Verilog.
- Programming skills: C, C++, assembly, Perl, makefile generation.
- Tools: RTL Simulators, eg VCS.
Responsibility includes the development of Verification Testbenches and automation, creation of tests – both directed and random, functional coverage model creation and report analysis, code coverage analysis, development of C-models, resolving mismatches between design and C-model, integration of third-party and internal verification IP, regression management, review and improvement of verification test suites.
How to Apply?
Interested applicants can apply for the internship through this link.
For full notification, click the link below.