The course aims at providing a comprehensive coverage of techniques for designing efficient VLSI architectures for DSP. Towards this, architectural optimization both at block level as well as at logic level will be considered. The key issues that will be taken up are as follows:
- Graphical Representation of DSP Algorithms
- Retiming for Throughput Maximization
- Pipelined and Parallel Filter Structures
- Bit Serial Digital Filters
- Distributed Arithmetic and Multiplierless Realization of Digital Filters
- Redundant Arithmetic
- DSP Architectures: Datapath and Control
- Speed Power Area Accuracy Tradeoff
- Synchronous vs. Asynch. Designs
- Memory Bandwidth Management
- DSP for Embedded Applications
The course also intends to have a few lab sessions in order to demonstrate digital design flow on Field Programmable Gate Array (FPGA), where the following modules may be covered.
- Behavioural and structural description for design representation and design entry.
- Validation through functional simulation.
- Partitioning, Placement and Routing.
- Post routing simulation for performance analysis.
- FPGA specific structural optimization with respect to speed and area.
- Configuration bitstream generation for actual implementation on FPGA.
The course may be viewed as a consolidated form of a semester long, graduate course on VLSI DSP system/architecture design. Participants from academia may thus find the course to be useful to develop similar courses at their respective institutions.
Alternatively, the course may also be used as a reference by industrial professionals interested in VLSI design of signal processing and communication systems. The course assumes minimal prerequisites. An undergraduate level knowledge of digital circuit design and elementary DSP operations is sufficient for one to be able to attend the course.
- 10,000.00 for teachers from universities/ colleges.
- 17,000.00 for people from industry.
- 15,000.00 for engineers/scientists from Defence Laboratories and ISRO
- 7,000.00 for students/research scholars [please enclose a bonafide certificate from parent institution].
How to Apply:
Interested persons may apply in the given format along with the registration fee, paid through a demand draft drawn in favour of ‘CEP-STC, IIT Kharagpur’ and payable at Kharagpur. The number of seats is limited and thus candidates are advised to register early.
Last date of registration: 10th June, 2017
Prof. Mrityunjoy Chakraborty
Dept. of Electronics & ECE
For more details, please visit this link.