Low power has emerged as a principal theme in today’s electronics industry. With the remarkable success and growth of the class of personal computing devices (portable desktops, audio- and video-based multimedia products) and wireless communications systems (personal digital assistants and personal communicators), the demand for high-speed computation and complex functionality with low power consumption has increased.
In the past, the major concerns of the VLSI designer were area, performance, cost, and reliability; power consideration was mostly of only secondary importance. In recent years, however, this has begun to change and power is being given comparable weight along with area and speed considerations.
Thus, the need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. Many issues are faced by designers at architectural, logic, circuit and device levels which are required to be overcome by efficient techniques. This course will address the latest trends and future challenges that must be met to design low power, high-performance systems.
The program will be designed around the following major topics:
- VLSI Design cycle
- Challenges at various design levels
- Power Estimation Methods
- Power reduction techniques at each design level
- Effects of scaling
- CMOS Analog design
- Digital circuit design
- CAD Techniques
- Nanoscale Semiconductor Devices
- Hands-on session on tools like Cadence and TCAD.
- Future Challenges
Experts from eminent organizations such as IITs, NITs, Industries will be invited for taking the expert lectures.
Interested candidates can request for participation in the course via email to firstname.lastname@example.org
Phone Number: 0172-2759648
Email ID: email@example.com