One of the major challenges for RF Engineers in today’s world is to minimize the electromagnetic interference (EMI) within circuits and systems due to increasing usage of high speed and high frequency devices. The electromagnetic compatibility (EMC) is mainly a technique to deal with such types of situations, where the main emphasis is to propose an optimum design in order to minimize the electromagnetic coupling and interference.
The main objective of this one week course is to provide the participants an insight into various techniques and procedures required for the design of electronic systems, which are in compliance with the EMC guidelines. The course would provide a brief outline of EMC guidelines prevalent in various geographical regions, and imposed by a number of agencies including the Bureau of Indian Standards (BIS). The concept of effective shielding using modern procedures involving the use of frequency selective surfaces(FSS)structures and light weight nanocomposites would be explained.
The participants would be exposed to the state of the art modeling and simulation software currently being used for EMI/EMC applications. Finally, it would be tried to provide a demonstration of experimental setups used for EMI/EMC applications.
Who can Attend
The course is designed for people from academia, R&D institutes and industry working in the field of RF, microwaves and high frequency digital electronics which requires design of EMI/EMC compatible circuits and systems.The course is equally suited for professionals and graduate students desirous of working in the challenging EMI/EMC field.
QIP Candidates:The teachers of the AICTE approved Engineering Colleges are eligible under this scheme. Faculty members from the streams of Electronics & Communication Engineering, and Electrical Engineering can apply under this program. The seats are limited, which would be filled on first come first serve basis and the candidate’s field of research interest.
How to Register
QIP Candidates: Application in the attached form should be sent to the coordinator with a caution deposit of Rs.1000 in the form of a cheque made payable to “Coordinator, Continuing Education Programme, IIT Kanpur”. The fee will be refunded for all participants who attend the course. The QIP participants will be paid TA/DA byA/C three tier for attending the course. The DA will be paid as per rules, adjusted against boarding and lodging at IIT, Kanpur.
Non-QIP participants and students can join the course by paying the registration fees through SBI Collect. The details of online payment are available here.
The application form is available here.
Industry/R&D Organizations: Rs. 20,000 +18% GST= Rs. 23,600
Academic Institutions (Non-QIP candidates): Rs. 10,000 +18% GST= Rs. 11,800
Students: Rs. 5,000 +18% GST = Rs.5,900
Last date for receipt of application: August 31, 2019
Acceptance Notification: September 14, 2019
Course Dates: October 9-13, 2019
Accommodation for non-student delegates would be arranged in the guest house of IIT, Kanpur depending upon the availability. The registration fee includes the boarding and food charges for non-QIP candidates under non-student category.
Dr. M. Jaleel Akhtar
Professor, ACES 326
Department of Electrical Engineering
Indian Institute of Technology Kanpur
Kanpur, UP – 208016
Phone: +91-(512)-259 6523